Single crystal wafer and solar battery cell

ABSTRACT

The present invention provides a single crystal wafer, wherein the main surface has a plane or a plane equivalent to a plane tilting with respect to a [100] axis of single crystal by angles of α (0°&lt;α&lt;90°) for the [011] direction, β (0°&lt;β&lt;90°) for the [01-1] direction and γ (0°≦γ&lt;45°) for the [10-1] or [101] direction. Thus, a single crystal wafer that can sufficiently bear device production processes even with a small wafer thickness is provided and thereby loss of single crystal raw material is reduced. Further, by using such a wafer, MIS type semiconductor devices and solar cells are provided at a low cost.

TECHNICAL FIELD

[0001] The present invention relates to a single crystal wafer used fordevice production processes, which can have a smaller thickness comparedwith conventional wafers, a MIS type semiconductor device and solar cellutilizing the wafer.

BACKGROUND ART

[0002] Single crystal wafers, of which typical examples are those ofsilicon (Si) and gallium arsenide (GaAs), are obtained by slicing asingle crystal ingot produced by the Czochralski method (CZ method) orthe floating zone method (FZ method) into wafers. Therefore, it isdesired to obtain wafers as many as possible from one ingot by makingthickness of wafer as small as possible or reducing the stock removalfor slicing. That is, desirability of reducing thickness of wafers orprocessing loss in the production of wafers to reduce waste of the rawmaterial and thereby reduce production cost of wafers has hitherto beenwidely recognized.

[0003] However, if thickness of wafer is simply reduced, it becomeslikely that breakage or chipping occurs in the wafer production processor device production process. Therefore, it is considered that wafersmust have a certain thickness (for example, about 700 to 800 μm in thecase of a silicon wafer having a diameter of 200 mm). Further, since alimitation is imposed on the reduction of stock removal for slicing byslicing apparatus, the reduction of stock removal for slicing suffersfrom a certain limit.

[0004] Furthermore, loss of the raw material is generated not only inthe wafer production process, but also in the device production process.Since the final thickness of wafer actually mounted as a chip is about100 to 200 μm, a step of reducing the thickness from the back surface(back lap) is used, and thus the raw material is wasted also in thisstep.

[0005] Meanwhile, a gate insulator film of MIS (metal/insulatorfilm/silicon) type transistor mainly produced by using a silicon singlecrystal wafer is required to have highly efficient electriccharacteristics and high reliability such as low leakage currentcharacteristic, low interface state density and high carrier injectionresistance. As a technique for forming a gate insulator film satisfyingthese requirements, there has conventionally been utilized the thermaloxidation technique using oxygen molecules or water molecules at 800° C.or higher. Conventionally, in order to obtain good oxide film/siliconinterface characteristics, oxide dielectric breakdown voltagecharacteristic and leakage current characteristic by using the thermaloxidation technique, there must be used a silicon wafer having a {100}plane for the surface or a silicon wafer having a plane orientationtilting by about 4° from a {100} plane of a single crystal.

[0006] If a gate oxide film is formed on a silicon wafer having a planeorientation other than those mentioned above by using the thermaloxidation technique, electric characteristics are degraded, that is, theinterface state density of oxide film/silicon interface becomes high,the oxide dielectric breakdown voltage characteristic and leakagecurrent characteristic are degraded and so forth. Therefore, as asilicon wafer on which semiconductor devices such as MIS typetransistors are formed, a silicon wafer having a {100} plane for thesurface or a silicon wafer having a plane orientation tilting by about4° from a {100} plane of a single crystal has conventionally been used.

[0007] However, in a silicon wafer having a {100} plane for the surface,a {110} plane serving as a cleavage plane exists perpendicularly to thesurface. Thus, breakages, chipping, slip dislocations and so forth arelikely to be caused during the process. Therefore, a usually usedsilicon wafer having a {100} plane for the surface has a thickness ofabout 700 to 800 μm for a diameter of 200 mm or a thickness of about 600to 700 μm for a diameter of 150 mm, and the same shall apply to asilicon wafer having a plane orientation tilting by about 4° from a{100} plane of a single crystal.

[0008] Recently, a technique was developed for forming an insulator filmof good quality irrespective of the plane orientation of silicon wafersurface (refer to 2000 Symposium ON VLSI Technology, Honolulu, Hi., Jun.13-15, 2000 “Advantage of Radical Oxidation for Improving Reliability ofUltra-Thin Gate Oxide”). Therefore, it can be said that, thanks to sucha technique, it became unnecessary to limit the plane orientation ofwafer for the production of MIS type semiconductor devices to the {100}surface.

DISCLOSURE OF THE INVENTION

[0009] Therefore, to effectively utilize the aforementioned technique offorming an insulator film of good quality irrespective of the planeorientation, an object of the present invention is to provide a singlecrystal wafer that can bear the device production process to a degreecomparable to those attained conventional wafers even with a smallerthickness of the water compared with those of the conventional wafers onthe basis of relationship between plane orientation and likeliness ofbreakage, and thereby reduce loss of single crystal. Another object ofthe present invention is to provide an MIS type semiconductor device ora solar cell, of which major problem is reduction of production cost, ata low cost by utilizing a silicon wafer having such a plane orientationunlikely to cause breakage.

[0010] The present invention that achieves the aforementioned objectsprovides a single crystal wafer, wherein the main surface has a plane ora plane equivalent to a plane tilting with respect to a [100] axis ofsingle crystal by angles of α (0°<α<90°) for the [011] direction, β(0°<β<90°) for the [01-1] direction and γ (0°≦γ<45°) for the [10-1] or[101] direction.

[0011] Since the surface of such a single crystal wafer has a planeorientation tilting with respect to all the {110} planes, at whichcleavage is likely to occur, it becomes more unlikely to suffer frombreakage due to an external stress compared with a conventional singlecrystal wafer having a {100} plane. Thus, wafers having a thicknesssmaller than those of conventional wafers can be produced. Therefore,number of wafers that can be produced from one single crystal ingot isincreased, and it becomes possible to reduce the cost.

[0012] The single crystal wafer of the present invention may consist ofsemiconductor silicon.

[0013] If the single crystal wafer consists of semiconductor silicon asdescribed above, the effect of the reduction of production cost becomeextremely significant, since semiconductor silicon is the most widelyused semiconductor at present.

[0014] The aforementioned single crystal wafer may satisfy arelationship of thickness of wafer (μm)/diameter of wafer (mm) ≦3.

[0015] Since the single crystal wafer of the present invention can haveexcellent mechanical strength as described above, it can be such anwafer having an extremely thin wafer thickness relative to diameter ofthe wafer that it should satisfy the relationship of thickness of wafer(μm)/diameter of wafer (mm) ≦3, which cannot be realized by theconventional techniques. Therefore, the effect provided by the reductionof production cost becomes more significant.

[0016] In the single crystal wafer of the present invention, aninsulator film is preferably formed on the surface of the single crystalwafer.

[0017] If an insulator film is formed on at least one surface of thesingle crystal wafer of the present invention as described above,cleavage of the wafer can be suppressed. If the insulator film is formedall over the wafer, the effect of suppressing the cleavage becomes moresignificant. Further, MIS semiconductor devices, for example, can beproduced by using such a wafer, and thus the devices can be produced ona thin wafer that is unlikely to break at a low cost.

[0018] In this case, the aforementioned insulator film is preferably asilicon oxide film containing Kr, or the aforementioned insulator filmis preferably a silicon nitride film containing Ar or Kr and hydrogen.

[0019] If the insulator film is a silicon oxide film containing Kr or asilicon nitride film containing Ar or Kr and hydrogen as describedabove, an insulator film of good quality can be obtained irrespective ofthe plane orientation.

[0020] Furthermore, a solar cell can be produced by using the singlecrystal wafer of the present invention described above.

[0021] Solar cells have not used so widely because of the highproduction cost thereof. Therefore, if the wafer of the presentinvention that has higher strength and enables processing of thinsilicon single crystal is used, the production cost of solar cells canbe reduced and it provides great advantages.

[0022] As described above, the single crystal wafer of the presentinvention can be a single crystal wafer that can bear the deviceproduction process to a degree comparable to those attained byconventional wafers even with a smaller thickness of the water comparedwith those of the conventional wafers. Therefore, loss of the singlecrystal raw material can be markedly reduced compared with conventionaltechniques, and by using such a silicon wafer, an MIS type semiconductordevice or a solar cell, of which major problem is reduction ofproduction cost, can be provided at a low cost.

BRIEF EXPLANATION OF THE DRAWINGS

[0023]FIG. 1 is an explanatory diagram for explaining plane orientationof the single crystal wafer of the present invention.

[0024]FIG. 2 shows an exemplary apparatus utilizing a radial line slotantenna for forming an oxide film on the single crystal wafer of thepresent invention.

[0025]FIG. 3 is a graph showing a relationship between oxide filmthickness containing Kr and oxidation time during oxidation of siliconwafer surface using Kr/O₂ high density plasma.

[0026]FIG. 4 is a graph showing the results of low frequency C-Vmeasurement for interface state density of oxide film.

BEAT MODE FOR CARRYING OUT THE INVENTION

[0027] Hereafter, the present invention will be explained in moredetail.

[0028] As described above, in response to the development of a techniquefor forming an insulator film of good quality irrespective of the planeorientation of silicon wafer surface, the inventors of the presentinvention noted the relationship between the plane orientation andlikeliness of breakage of wafer in order to utilize the technique. Thatis, since it became unnecessary to limit the plane orientation for thedevice characteristics, they conceived that, if a plane orientationproviding strength as high as possible was selected, wafers causingbreakage or chipping at a level comparable to those attained byconventional wafers could be obtained even if the wafers were producedwith a smaller thickness compared with those of the conventional wafers,and as a result, number of wafers obtainable from one ingot could beincreased.

[0029] Meanwhile, as for the plane orientation of silicon wafers onwhich devices are produced, while low index planes such as {100} planeand {111} plane have been used from old days, wafers having a planeorientation tilting from such plane orientation have also been used. Forexample, the inventions disclosed in Japanese Patent Laid-openPublication (Kokai) No. 56-109896, Japanese Patent Publication (Kokoku)No. 3-61634 and Japanese Patent Laid-open Publication No. 8-26891 useplanes tilting from a {100} plane or {111} plane by several degrees forone {110} plane. However, these planes tilt for only one {110} plane,and the wafers cannot be said to be wafers that are unlikely to break.Moreover, those techniques relate to prevention of generation ofprocess-induced crystal defects or prevention of generation of defectsduring epitaxial growth.

[0030] Further, Japanese Patent Laid-open Publication No. 9-262825discloses that, as for the relationship between the plane orientationand likeliness of breakage of wafer, when a single crystal is slicedwith a wire saw, wafers are likely to suffer from breakage if a saw markconforms to the cleavage direction. However, the cleavage planeconsidered in this reference is only the {110} plane orthogonal to the{100} plane, and the {110} plane having an angle of 45° with respect tothe {100} plane is not considered at all. Thus, all the sliced wafersare wafers having a low index plane such as {100} plane.

[0031] The inventors of the present invention conceived that, in orderto produce a wafer unlikely to break, consideration of only the {110}plane perpendicular to the {100} plane was insufficient, and it wasnecessary to consider the {110} plane having an angle of 45° withrespect to the {100} plane. Thus, the present invention wasaccomplished.

[0032] Hereafter, the present invention will be explained by referringto the appended drawings. However, the present invention is not limitedto these explanations.

[0033]FIG. 1 is a diagram for explaining plane orientation of the singlecrystal wafer of the present invention. The arrowhead (vector)represented by the bold line in FIG. 1 indicates the plane orientationof the single crystal wafer of the present invention (orientation of thenormal of the wafer surface). It has, with respect to the [100] axis(X-axis), tilting angles of α (0°<α<90°) for the [011] direction, β(0°<β<90°) for the [01-1] direction and γ (0°≦γ<45°) for the [10-1]direction.

[0034] That is, the single crystal wafer having this plane orientationwill have a plane tilting by angles of α, β and γ from the cleavageplanes, (011) plane, (01-1) plane and (10-1) plane, respectively, andthus mechanical strength of the wafer with respect to an external stressis increased compared with conventional wafers having a low index planeorientation.

[0035] In this case, if α=β, γ becomes 0°. If a cross section of a waferhaving such a tilting plane is observed from the [010] direction, thecleavage planes, the (10-1) plane and (101) plane, are bilaterallysymmetrical planes having an angle of 45° with respect to the (100)plane, respectively. Therefore, if the number of effective bonds of thecrystal does not show significant difference for all of the planeorientations, it is considered that the strength becomes highest whenγ=0°. However, it is considered that actual strength is determined byboth of the plane orientation and number of effective bonds, and thus γof 0° cannot be said to be always optimal since the number of effectivebonds differs depending on the plane orientation. Therefore, even when γsatisfies the condition of 0°<γ<45°, high strength can be obtained.Incidentally, it is known that the numbers of effective bonds in thecase of silicon single crystal are 11.8 ×10¹⁴ numbers/cm², 9.6 ×10¹⁴numbers/cm² and 6.8 ×10¹⁴ numbers/cm² for the (111), (110) and (100)planes, respectively.

[0036] Further, when α×β, γdoes not mean an tilting angle for the [10-1]direction shown in FIG. 1, but means a tilting angle for the [101]direction.

[0037] In addition, as a plane orientation equivalent to that of thesingle crystal wafer shown in FIG. 1, there are three planes in thedirections corresponding to those obtained by revolving the vector shownin FIG. 1 by 90° at a time on the y-z plane.

[0038] In order to produce a wafer having such a particular tiltingplane, a single crystal ingot produced under ordinary condition can besliced with a predetermined angle. In the case of silicon singlecrystal, ingots ordinarily produced have a crystal orientation of <100>or <111>, and <110> and <511> are known as crystal orientations thatenable crystal production without causing unacceptable deformation ofcrystal. Further, by using a seed crystal preliminarily provided with anoff angle of several degrees or so as a seed crystal used at the time ofpulling a single crystal, a crystal having an off angle can be pulled.Therefore, by using such a crystal, adjustment of the orientation at thetime of slicing can also be simplified.

[0039] Since the surface of the single crystal wafer of the presentinvention described above has a plane orientation tilting from all ofthe {110} planes along which cleavage is likely to occur, a wafer thatis more unlikely to break with an external stress and has a smallerthickness compared with conventional wafers having {100} planes can beproduced.

[0040] For example, when a single crystal wafer is produced fromsemiconductor silicon, it is necessary to produce a wafer having athickness of about 700 to 800 μm in the case of a conventional siliconwafer having a diameter of 200 mm. However, in the single crystal waferof the present invention, the thickness can be made thinner than theabove, and it is also possible to obtain a thickness of less than 600 μmin the case of a silicon wafer having a diameter of 200 mm, for example.Therefore, number of wafers that can be produced from one single crystalingot is increased, and it becomes possible to reduce the productioncost.

[0041] Hereafter, the method for forming a gate insulator film requiredfor MIS type semiconductor devices by using a silicon wafer having sucha tilting plane (referred to as “(abc) plane” hereinafter) will beexplained.

[0042] If an insulator film is formed by the method described below, aninsulator film having characteristics as a gate insulator filmcomparable to those of conventional films and showing no dependency onthe plane orientation can surely be formed.

[0043]FIG. 2 shows an exemplary apparatus utilizing a radial line slotantenna for forming an oxide film on the single crystal wafer of thepresent invention. This embodiment has a novel characteristic that Kr isused as plasma excitation gas for the oxide film formation. Inside of avacuum chamber (processing chamber) 1 is made vacuum, and Kr gas and O₂gas are introduced from a shower plate 2 to adjust the pressure in theprocessing chamber to be about 1 Torr (about 133 Pa).

[0044] A circular substrate 3 such as a silicon wafer is placed on asample stand 4 having a heating mechanism, and temperature is adjustedso that the temperature of the sample should become 400° C. Thistemperature may be in the range of 200 to 550° C. From a coaxial waveguide 5, a microwave of 2.45 GHz is supplied to the processing chambervia a radial line slot antenna 6 and a dielectric plate 7 to generatehigh density plasma in the processing chamber. Further, any frequency ofthe supplied microwave may be selected so long as it is in the range of900 MHz to 10 GHz.

[0045] A spacing between the shower plate 2 and the substrate 3 isadjusted to 6 cm in this embodiment. A narrower spacing enables filmformation with a higher rate. Although an example of film formationusing a plasma apparatus utilizing a radial line slot antenna was shownin this embodiment, a microwave may be introduced into the processingchamber by using another method.

[0046] In the high density excitation plasma in which Kr gas and O₂ gasare mixed, Kr* and O₂ molecules in an intermediate excited state collideeach other, and thus atomic oxygen O* generates efficiently. Thesubstrate surface is oxidized with this atomic oxygen. The conventionaloxidation of silicon surface is attained by H₂O molecules and/or O₂molecules, and the treatment temperature is extremely high, i.e., 800°C. or higher. However, the oxidation by atomic oxygen according to thepresent invention may be realized at a sufficiently low temperature,i.e., 550° C. or lower.

[0047] Although higher pressure in the processing chamber is desirablefor increasing occasions of collision of Kr* and O₂, O* will collideeach other and return into a O₂ molecule at an unduly high pressure. Theinventors of the present invention measured thickness of oxide filmgrown by oxidation treatment of 10 minutes at a silicon substratetemperature of 400° C. with keeping pressure ratios of 97% for Kr and 3%for oxygen in the processing chamber and a varying gas pressure in theprocessing chamber. As a result, the thickness of oxide film became thelargest when the gas pressure in the processing chamber was 1 Torr, andthus it was found that oxidation condition of that pressure or pressurearound that was preferred. It was found that this pressure condition wassimilarly preferred for the (abc) plane as well as the (100) plane andthe (111) plane.

[0048]FIG. 3 shows a relationship between oxide film thicknesscontaining Kr and oxidation time during oxidation of silicon wafersurface using Kr/O₂ high density plasma. The graph shows the results forsilicon substrates having a plane orientation of (100) plane, (111)plane or (abc) plane. FIG. 3 also shows oxidation time dependency inconventional dry thermal oxidation at 900° C. It is evident that theoxidation rate in the Kr/O₂ high density plasma oxidation at a substratetemperature of 400° C. and a processing chamber pressure of 1 Torr ishigher than the oxidation rate in the dry O₂ oxidation at a substratetemperature of 900° C. and atmospheric pressure.

[0049] By using the silicon substrate surface oxidation with Kr/O₂ highdensity plasma, the productivity of surface oxidation technique can alsobe markedly improved. In the conventional high temperature oxidationtechnique, O₂ molecules or H₂O molecules pass through an oxide filmformed on a surface by diffusion and reach the interface ofsilicon/silicon oxide film to contribute to the oxidation. Therefore, itis a common knowledge that the oxidation rate is rate-determined by thediffusion rates of O₂ molecules or H₂O molecules through the oxide film,and it increases with a factor of t^(1/2) as a function of oxidationtime t. However, in the Kr/O₂ high density plasma oxidation according tothe present invention, the oxidation rate is linear until the oxide filmthickness reaches 35 nm. This means that the diffusion rate of atomicoxygen in the silicon oxide film is extremely high, and atomic oxygencan freely pass through the silicon oxide film.

[0050] Kr density distribution along the depth direction in a siliconoxide film formed by the aforementioned procedure was investigated byusing a total reflection X-ray fluorescence spectrophotometer. Krdensity decreased in a region having a thinner oxide film thickness, andKr existed at a density of about 2×10¹¹ cm⁻² at a silicon oxide filmsurface. That is, in this silicon film, the Kr concentration in the filmis constant for the film thickness of 4 nm or more, and the Krconcentration decreases towards the silicon/silicon oxide filminterface.

[0051]FIG. 4 shows the results of low frequency C-V measurement forinterface state density of an oxide film. The silicon oxide film wasformed at a substrate temperature of 400° C. by using the apparatusshown in FIG. 2. The partial pressure of oxygen in rare gas was fixed to3%, and the pressure in the processing chamber was fixed to 1 Torr. Forcomparison, the interface state density of a thermal oxide film formedat 900° C. in an atmosphere of 100% oxygen is also shown. The interfacestate density of the oxide film formed by using Kr gas was low for allof the (100) plane, (111) plane and (abc) plane and equivalent to theinterface state density of the thermal oxide film formed at 900° C. in adry oxidation atmosphere so as to have a (100) plane. Thus, it can beseen that an oxide film of good quality showing a low interface statedensity can similarly be obtained for the (abc) plane. In addition, theinterface state density of the thermal oxide film formed with the (111)plane is larger by 1 digit order compared with them. The interface statedensity referred to in the present invention means interface trapdensity (Dit) in the mid gap, and it is obtained by the quasi-static C-Vtechnique (quasi-static capacitance-voltage technique).

[0052] As for electric characteristics and reliability characteristicsof the oxide film such as dielectric breakdown voltage, leakagecharacteristic, hot carrier resistance and charge quantity causingbreakdown of silicon oxide film upon flowing a stress current, QBD(Charge-to-Breakdown), the oxide film obtained by the silicon substratesurface oxidation using Kr/O₂ high density plasma showed favorablecharacteristics comparable to those obtained for the oxide film obtainedby the thermal oxidation at 900° C.

[0053] As described above, although the oxide film grown with the Kr/O₂high density plasma was oxidized at a low temperature of 400° C., itshowed characteristics comparable to or superior to those shown by theconventional oxide film of a (100) plane obtained by the hightemperature thermal oxidation, even for the (abc) plane, without beinginfluenced by the plane orientation. These advantages are partlyprovided by Kr contained in the oxide film. It is considered that whenKr is contained in the oxide film, stress in the film or at the Si/SiO₂interface is relaxed, charges in the film and the interface statedensity are reduced, and thereby the electric characteristics of thesilicon oxide film are markedly improved. It is considered that, inparticular, Kr contained at a level of 5×10¹¹ cm⁻² or less in theconcentration of the surface contributes to the improvements of theelectric characteristics and reliability characteristics of the siliconoxide film.

[0054] The MIS transistor utilizing this gate oxide film shows favorablecharacteristics in any plane orientation, and characteristics equivalentto those obtained with the (100) plane can be obtained even with the(abc) plane.

[0055] In addition, in order to produce the oxide film of the presentinvention, other than the apparatus shown in FIG. 2, an apparatus forplasma process that enables low temperature oxide film formation usingplasma may also be used.

[0056] For example, an oxide film can also be formed by a two-stageshower plate type plasma process apparatus having first gas dischargingmeans for discharging Kr gas for exciting plasma by a microwave andsecond gas discharging means for discharging oxygen gas, which isdifferent from the first gas discharging means.

[0057] Hereafter, low temperature nitride film formation using plasmawill be explained. A nitride film forming apparatus is almost the sameas the apparatus shown in FIG. 2. In this embodiment, Ar or Kr is usedas plasma excitation gas for the nitride film formation. Inside of thevacuum chamber (processing chamber) 1 is made vacuum, and Ar gas and NH₃gas are introduced from the shower plate 2 to adjust the pressure in theprocessing chamber to be about 100 mTorr. A circular substrate 3 such asa silicon wafer is placed on the sample stand 4 having a heatingmechanism, and temperature is adjusted so that the temperature of thesample should become 500° C. This temperature may be adjusted to be inthe range of about 200 to 550° C.

[0058] From the coaxial wave guide 5, a microwave of 2.45 GHz issupplied to the processing chamber via the radial line slot antenna 6and the dielectric plate 7 to generate high density plasma in theprocessing chamber. The frequency of the supplied microwave may be inthe range of 900 MHz to 10 GHz. A spacing between the shower plate 2 andthe substrate 3 is adjusted to 6 cm in this example. A narrower spacingenables film formation with a higher rate.

[0059] Although an example of film formation using a plasma apparatusutilizing a radial line slot antenna was shown in this embodiment, amicrowave may be introduced into the processing chamber by using anothermethod. Further, although Ar is used as the plasma excitation gas, useof Kr can also provide similar results. Furthermore, although NH₃ isused as the plasma process gas, a mixed gas of N₂ and H₂ or the like mayalso be used.

[0060] In the high density excitation plasma of a mixed gas of Ar or Krand NH₃ (or N₂, H₂), NH* radicals are efficiently generated by Ar* orKr* in an intermediate excited state. With these NH* radicals, thesubstrate surface is nitrided. Such nitriding of silicon enablesformation of nitride film of high quality at a low temperature withoutlimitation of the plane orientation of silicon.

[0061] In the silicon nitride film formation according to the presentinvention, one of the important requirements is the presence ofhydrogen. When hydrogen exists in the plasma, dangling bonds in thesilicon nitride film or at the interface form Si-H and N-H bonds tocause termination, and as a result, electronic traps in the siliconnitride film and at the interface are eliminated. The presence of theSi-H bonds and N-H bonds in the nitride film of the present inventionhas been confirmed by infrared absorption spectrometry and X-rayphotoelectron spectrometry of the film. The presence of hydrogen alsoeliminates the hysteresis of CV characteristics and suppresses thesilicon/silicon nitride interface state density as low as 3 ×10¹⁰ eV⁻¹cm⁻². In the formation of the silicon nitride film by using a rare gas(Ar or Kr) and a mixed gas of N₂/H₂, if the hydrogen gas is used at apartial pressure of 0.5% or more, electron and hole traps in the filmare sharply decreased.

[0062] Relative dielectric constant of the silicon nitride film of thisembodiment was 7.9, which is twice as large as that of the silicon oxidefilm.

[0063] In order to produce the nitride film of the present invention,other than the apparatus shown in FIG. 2, an apparatus for plasmaprocess that enables low temperature nitride film formation using plasmamay also be used. For example, the nitride film can also be formed by atwo-stage shower plate type plasma process apparatus having first gasdischarging means for discharging Ar or Kr gas for exciting plasma by amicrowave and second gas discharging means for discharging NH₃ (or N₂/H₂gas) gas, which is different from the first gas discharging means.

[0064] Hereafter, a method for producing a solar cell by using a siliconwafer having an (abc) plane such as the wafer of the present inventionwill be explained.

[0065] As already described, a silicon wafer having an (abc) plane asthe main surface shows high mechanical strength. Therefore, it becomespossible to slice a silicon single crystal ingot for solar cells with athickness smaller than the thickness used in the slicing of conventionalsilicon single crystal ingot for solar cells (about 400 to 600 μm for adiameter of 100 to 150 mm), and the thickness can be, for example, 300to 450 μm or less than the foregoing range for a diameter of 100 to 150mm. Therefore, the yield of wafers is improved for the thickness madethinner, and thus it becomes possible to reduce the cost.

[0066] The slicing is performed by using a wire saw or an inner diameterslicer, and damage is generated in a crystal by mechanical impact at thetime of the slicing. Such damage degrades electric characteristics ofwafers and also affect characteristic of the cell. Therefore, in orderto eliminate such a damage layer, chemical etching is performed forabout 10 to 20 μm. Such etching is usually performed by using a mixedacid of HF and HNO₃, and several tens of wafers are put into a carrierfor etching to perform the etching with rotating the carrier in order toattain uniform etching over the surfaces. Therefore, higher waferstrength is advantageous for such an etching process, since wafers areunlikely to break even with a small thickness. Further, etching with analkali for increasing conversion efficiency, called texture treatment,is also performed.

[0067] Then, since a p-type silicon wafer is usually used, n-typeimpurities are diffused in the wafer to form a pn junction, and thewafer is subjected to formation of electrodes and formation ofantireflection film to produce a solar cell.

[0068] By successively forming a n-type layer, p-type layer and n-typelayer on a surface of a p-type wafer by epitaxial growth to produce apnpn type tandem structure, a conversion efficiency of 20% or more andan output voltage of 1.5 V can be attained.

[0069] As described above, the wafer of the present invention having the(abc) plane as the main surface can sufficiently bear the productionsteps of devices and solar cells even with a smaller thickness, and thusit enables marked reduction of the production cost.

[0070] The present invention is not limited to the embodiments describedabove. The above-described embodiments are mere examples, and thosehaving the substantially same structure as that described in theappended claims and those providing similar functions and advantages areall included in the scope of the present invention.

[0071] For example, while single crystal wafers consisting ofsemiconductor silicon are exemplified in the aforementioned embodiments,the present invention is not limited to these and can be applied tosingle crystals other than silicon and compound semiconductors, and suchapplication also falls within the scope of the present invention.

1. A single crystal wafer, wherein the main surface has a plane or aplane equivalent to a plane tilting with respect to a [100] axis ofsingle crystal by angles of α (0°<α<90°) for the [011] direction, β(0°<β<90°) for the [01-1] direction and γ (0°≦γ<45°) for the [10-1] or[101] direction.
 2. The single crystal wafer according to claim 1, whichconsists of semiconductor silicon.
 3. The single crystal wafer accordingto claim 1 or 2, which satisfies a relationship of thickness of wafer(μm)/diameter of wafer (mm) ≦3.
 4. A single crystal wafer, wherein aninsulator film is formed on a surface of the single crystal waferaccording to claim 2 or
 3. 5. The single crystal wafer according toclaim 4, wherein the insulator film is a silicon oxide film containingKr.
 6. The single crystal wafer according to claim 4, wherein theinsulator film is a silicon nitride film containing Ar or Kr andhydrogen.
 7. A solar cell produced by using the single crystal waferaccording to any one of claims 1 to 6.